Espressif Systems /ESP32 /EMAC_DMA /DMAMISSEDFR

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Interpret as DMAMISSEDFR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MISSED_FC0 (OVERFLOW_BMFC)OVERFLOW_BMFC 0OVERFLOW_FC0 (OVERFLOW_BFOC)OVERFLOW_BFOC

Description

Missed Frame and Buffer Overflow Counter Register

Fields

MISSED_FC

This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.

OVERFLOW_BMFC

This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened.

OVERFLOW_FC

This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.

OVERFLOW_BFOC

This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.

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